library verilog;
use verilog.vl_types.all;
entity main is
    port(
        clk             : in     vl_logic;
        mode            : in     vl_logic;
        \select\        : in     vl_logic;
        set             : in     vl_logic;
        rst             : in     vl_logic;
        stop            : in     vl_logic;
        s_data          : out    vl_logic_vector(7 downto 0);
        m_data          : out    vl_logic_vector(7 downto 0);
        h_data          : out    vl_logic_vector(7 downto 0);
        beep            : out    vl_logic
    );
end main;
